-----------------------------------------------
-- Project		: ECE 251 FINAL PROJECT
-- Author 		: Mahmut Yilmaz
-- Last Modified: 04/13/2007
-----------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.all;

ENTITY packetgen_8_simple IS
	PORT (	clock_eth		: IN  STD_LOGIC;	-- PosEdge Clock used	
			clock_crc		: IN  STD_LOGIC;	-- PosEdge Clock used
			enable			: IN  STD_LOGIC;
			start			: IN  STD_LOGIC;	
      		random_out		: OUT STD_LOGIC 	-- output pseudo-random number & CRC
			);
END packetgen_8_simple;

ARCHITECTURE struct OF packetgen_8_simple IS
	COMPONENT lfsr8
		PORT (	clock			: IN  STD_LOGIC;	-- PosEdge Clock used	
				reset			: IN  STD_LOGIC;	-- Resets all flops to 0, active HIGH
	      		q	 			: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- output pseudo-random number
				polynomial		: IN  STD_LOGIC_VECTOR(7 DOWNTO 0); -- set LFSR polynomial
																	-- it is recommended to set shift_enable='0'
																	-- before changing the polynomial
				seed 			: IN  STD_LOGIC_VECTOR(7 DOWNTO 0); -- seed to LFSR
																	-- it is recommended to set shift_enable='0'
																	-- before changing the polynomial
				seed_change		: IN  STD_LOGIC;	-- Enable seed change. Resets all flops first.
				shift_enable	: IN  STD_LOGIC 	-- Enable shift & pseudo-random number generation, active HIGH
				);
	END COMPONENT;		
	
	COMPONENT crc32_d8 IS
		PORT (	clk     : IN  STD_LOGIC;
		        reset   : IN  STD_LOGIC;
		        enable  : IN  STD_LOGIC;
		        init    : IN  STD_LOGIC;
		        data_in : IN  STD_LOGIC_VECTOR (7 DOWNTO 0);
		        crc_out : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
				);
	END COMPONENT;
	
	COMPONENT par2ser_8bit IS
		PORT (	clock			: IN  STD_LOGIC;	-- PosEdge Clock used	
				reset			: IN  STD_LOGIC;	-- Reset input
				enable			: IN  STD_LOGIC;	-- Enable
				input			: IN  STD_LOGIC_VECTOR (7 DOWNTO 0);	-- Input
	      		q	 			: OUT STD_LOGIC 	-- Output
				);
	END COMPONENT;
	
	COMPONENT par2ser_32bit IS
		PORT (	clock			: IN  STD_LOGIC;	-- PosEdge Clock used	
				reset			: IN  STD_LOGIC;	-- Reset input
				enable			: IN  STD_LOGIC;	-- Enable
				input			: IN  STD_LOGIC_VECTOR (31 DOWNTO 0);	-- Input
	      		q	 			: OUT STD_LOGIC 	-- Output
				);
	END COMPONENT;
	
	COMPONENT mux21 IS
		PORT (	in0,in1			: IN  STD_LOGIC;	-- Multiplexer inputs	
				sel				: IN  STD_LOGIC;	-- Multiplexer select
	      		q_m	 			: OUT STD_LOGIC 	-- Multiplexer output
				);
	END COMPONENT;
	

	-- Internal signals
	SIGNAL lfsr_clock:STD_LOGIC; 
	SIGNAL lfsr_reset:STD_LOGIC; 
	SIGNAL lfsr_q:STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL lfsr_polynomial:STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL lfsr_seed:STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL lfsr_seed_change:STD_LOGIC; 
	SIGNAL lfsr_shift_enable:STD_LOGIC; 
	SIGNAL crc32_clock:STD_LOGIC;
	SIGNAL crc32_reset:STD_LOGIC;
	SIGNAL crc32_enable:STD_LOGIC;
	SIGNAL crc32_init:STD_LOGIC;
	SIGNAL crc32_data_in:STD_LOGIC_VECTOR (7 DOWNTO 0);
	SIGNAL crc32_crc_out:STD_LOGIC_VECTOR (31 DOWNTO 0);
	SIGNAL counter_clock:STD_LOGIC;
	SIGNAL counter_clear:STD_LOGIC;
	SIGNAL counter_count:STD_LOGIC;
	SIGNAL counter_q:STD_LOGIC_VECTOR(15 DOWNTO 0);
	SIGNAL comparator_in0:STD_LOGIC_VECTOR (15 DOWNTO 0);
	SIGNAL comparator_in1:STD_LOGIC_VECTOR (15 DOWNTO 0);
	SIGNAL comparator_q:STD_LOGIC;
	SIGNAL par2ser8_clock:STD_LOGIC; 
	SIGNAL par2ser8_reset:STD_LOGIC; 
	SIGNAL par2ser8_enable:STD_LOGIC; 
	SIGNAL par2ser8_input:STD_LOGIC_VECTOR (7 DOWNTO 0); 
	SIGNAL par2ser8_q:STD_LOGIC; 
	SIGNAL par2ser32_clock:STD_LOGIC; 
	SIGNAL par2ser32_reset:STD_LOGIC; 
	SIGNAL par2ser32_enable:STD_LOGIC; 
	SIGNAL par2ser32_input:STD_LOGIC_VECTOR (31 DOWNTO 0); 
	SIGNAL par2ser32_q:STD_LOGIC; 
	SIGNAL mux_in0:STD_LOGIC;
	SIGNAL mux_in1:STD_LOGIC;
	SIGNAL mux_sel:STD_LOGIC; 
	SIGNAL mux_q:STD_LOGIC; 	
BEGIN
	x_lfsr: lfsr8 PORT MAP (clock=>lfsr_clock,reset=>lfsr_reset,q=>lfsr_q,polynomial=>lfsr_polynomial,
				seed=>lfsr_seed,seed_change=>lfsr_seed_change,shift_enable=>lfsr_shift_enable);	

	x_crc:  crc32_d8 PORT MAP (clk=>crc32_clock,reset=>crc32_reset,enable=>crc32_enable,init=>crc32_init,
				data_in=>crc32_data_in,crc_out=>crc32_crc_out);
	
	x_counter: counter_16 PORT MAP (clock=>counter_clock,clear=>counter_clear,count=>counter_count,
				q=>counter_q);
	
	x_comparator: comparator_16 PORT MAP (in0=>comparator_in0,in1=>comparator_in1,q=>comparator_q);
	
	x_mux: mux21 PORT MAP (in0=>mux_in0, in1=>mux_in1, sel=>mux_sel, q_m=>mux_q);
	
	x_par2ser_8bit: par2ser_8bit PORT MAP (clock=>par2ser8_clock, reset=>par2ser8_reset, 
				enable=>par2ser8_enable, input=>par2ser8_input, q=>par2ser8_q);

	x_par2ser_32bit: par2ser_32bit PORT MAP (clock=>par2ser32_clock, reset=>par2ser32_reset, 
				enable=>par2ser32_enable, input=>par2ser32_input, q=>par2ser32_q);
				
	x_fsm:  fsm_packetgen_8 PORT MAP ( gl_ref_clock_crc=>clock_crc,gl_ref_clock_eth=>clock_eth,gl_enable=>enable,
				gl_start=>start,gl_n_bytes=>N,gl_output=>random_out,
				lfsr_clock=>lfsr_clock,lfsr_reset=>lfsr_reset,lfsr_q=>lfsr_q,
				lfsr_polynomial=>lfsr_polynomial,lfsr_seed=>lfsr_seed,
				lfsr_seed_change=>lfsr_seed_change,lfsr_shift_enable=>lfsr_shift_enable,
				crc32_clock=>crc32_clock,crc32_reset=>crc32_reset,crc32_enable=>crc32_enable,
				crc32_init=>crc32_init,crc32_data_in=>crc32_data_in,crc32_crc_out=>crc32_crc_out,
				counter_clock=>counter_clock,counter_clear=>counter_clear,
				counter_count=>counter_count,counter_q=>counter_q,comparator_in0=>comparator_in0,
				comparator_in1=>comparator_in1,comparator_q=>comparator_q,
				par2ser8_clock=>par2ser8_clock,par2ser8_reset=>par2ser8_reset,
				par2ser8_enable=>par2ser8_enable,par2ser8_input=>par2ser8_input,
				par2ser8_q=>par2ser8_q,par2ser32_clock=>par2ser32_clock,
				par2ser32_reset=>par2ser32_reset,par2ser32_enable=>par2ser32_enable,
				par2ser32_input=>par2ser32_input,par2ser32_q=>par2ser32_q,mux_in0=>mux_in0,
				mux_in1=>mux_in1,mux_sel=>mux_sel,mux_q=>mux_q);	
	
END struct;